How is POPCNT implemented in hardware?

Question

According to http://www.agner.org/optimize/instruction_tables.pdf, the POPCNT instruction (which returns the number of set bits in a 32-bit or 64-bit register) has a throughput of 1 instruction per clock cycle on modern Intel and AMD processors. This is much faster than any software implementation which needs multiple instructions (How to count the number of set bits in a 32-bit integer?).

How is POPCNT implemented so efficiently in hardware?

Answer 1

There's a patent for combined popcnt, bit scan forward / reverse:

US8214414 B2 - Combined set bit count and detector logic

Abstract

A merged datapath for PopCount and BitScan is described. A hardware circuit includes a compressor tree utilized for a PopCount function, which is reused by a BitScan function (e.g., bit scan forward (BSF) or bit scan reverse (BSR)). Selector logic enables the compressor tree to operate on an input word for the PopCount or BitScan operation, based on a microprocessor instruction. The input word is encoded if a BitScan operation is selected. The compressor tree receives the input word, operates on the bits as though all bits have same level of significance (e.g., for an N-bit input word, the input word is treated as N one-bit inputs). The result of the compressor tree circuit is a binary value representing a number related to the operation performed (the number of set bits for PopCount, or the bit position of the first set bit encountered by scanning the input word).