how implement store byte and store half-word in realistic approach

Question

i'm implementing an instance of single cycle MIPS processor. i want to implement store half-word and store byte

I've added a new input signal to my "Data memory" to control what to store like the code below.

// this was prof. Harris implementation in "digital design and computer 
// architecture book" implementation before i turn the "we" (Write Enable) signal into 2 bits  

module dmem(input logic clk, [1:0]we, //where we is an output of the control unit
            input logic [31:0] a, wd, 
            output logic [31:0] rd);

logic [31:0] RAM[63:0];

assign rd = RAM[a[31:2]]; // word aligned

always_ff @(posedge clk)
    case(we)
        2'b01: RAM[a[31:2]] <= wd; // sw 
        2'b10: RAM[a[31:0]][15:0] <= wd[15:0]; // sh
        2'b11: RAM[a[31:0]][7:0] <= wd[7:0]; // sb
        default:
        // do nothing
        ...

is this realistic if it's not what is the conventional way to implement it?

I'm studying it as a hobby, sorry if my question seems to be stupid

Answer 1

The main index for the RAM must always be the word address. I am assuming half-word write can upper and lower portions of the word, and byte write can assign to any byte within the word.

You can use the +: slice operator (See Indexing vectors and arrays with +:) to assign a portion of the word

always @(posedge clk) // NOTE: always_ff is SystemVerilog
  case(we)
    2'b01: RAM[a[31:2]] <= wd; // sw 
    2'b10: RAM[a[31:2]][ {a[1],4'b0000} +: 16] <= wd[15:0]; // sh
    2'b11: RAM[a[31:2]][ {a[1:0],3'b000} +: 8] <= wd[7:0]; // sb
    default:
    // do nothing
  endcase

With SystemVerilog, there is also the option of multi-dimensional packed arrays

//    [shw][sby][dat]    [sw  ]
logic [1:0][1:0][7:0] RAM[63:0];

assign rd = RAM[a[31:2]]; // word aligned

always_ff @(posedge clk)
  case(we)
    2'b01: RAM[a[31:2]] <= wd; // sw 
    2'b10: RAM[a[31:2]][a[1]] <= wd[15:0]; // sh
    2'b11: RAM[a[31:2]][a[1]][a[0]] <= wd[7:0]; // sb
    default:
    // do nothing
  endcase

I don't know how well most synthesizers will treat multi-dimensional packed arrays. Any synthesizer compatible with IEEE1364-2001 or latter will support +:, however I have seen mix results in how efficient the results are compared nested case statements. You will need to experiment.