How to write case insensitive Lex pattern rules?

Question

Structure of my file is,

`pragma TOKEN1_NAME TOKEN1_VALUE
`pragma TOKEN2_NAME TOKEN2_VALUE
`pragma TOKEN3_NAME TOKEN3_VALUE
`pragma TOKEN4_NAME TOKEN4_VALUE
 TEXT{

 // A valid VHDL or verilog
 }
`pragma TOKEN2_NAME TOKEN2_VALUE
 TEXT{

   // VHDL or verilog
 }

Since i am dealing with both Verilog and VHDL.I need to restructure my token names by taking into mind that VHDL is case insensitive. I want to use single parser for both the cases.What can be the most efficient way for the same ? Do flex support some sort of functionality to allow case insensitive pattern match and we can later check if token names are sanitized(having all small letters),if the format of the file is Verilog ?

Answer 1

Flex supports case-insensitivity inside patterns using the syntax:

(?i:...)

The pattern between the : and the ) will be scanned without regard to case.

This does not imply that the input is "sanitized", turned into lower-case, or modified in any way. That is your responsibility, if you want to do so. All it means is that (for example):

(?i:KeyWord)

will match any of the inputs KEYWORD, keyword, kEywOrd, etc.

If you have an ancient flex version (older than 2.5.34, released at the end of 2007) and for some reason you don't want to upgrade, you'll need to get used to writing patterns like this:

[Kk][Ee][Yy][Ww][Oo][Rr][Dd]

which you will still find examples of in older scanner definition files.