How come `0F 1A /r` and `0F 1B /r` have been NOP before Intel MPX?

Question

On processors which don't support Intel MPX the documentation says that all MPX instructions are NOP. Namely, as I've looked through all these instructions, they all appear to be 0F 1A /r or 0F 1B /r unprefixed or prefixed with F3, F2 or 66 bytes, depending on the instruction. Also, there are statements like for BNDMK:

The reg-reg form of this instruction retains legacy behavior (NOP).

I've tried to search these opcodes in PDF (namely my search string was 0F 1), but all I found there was only description of MPX instructions. Looking in Instruction Set Reference from February 2014, I've found lots of instructions of this form, but they were not NOPs, e.g. F2 0F 12 /r is MOVDDUP. And looking specifically for 0F 1A and 0F 1B I failed to find anything there.

Looking for NOP I found multibyte NOP 0F 1F /0, but it doesn't coincide with MPX instructions form.

So my question is, where is it documented that the legacy behavior of 0F 1A /r and 0F 1B /r is NOP? Is it some general rule for this form of instructions, or maybe they represent some non-NOP instruction in NOP form (like 90 standing for xchg eax,eax)?

Answer 1

The intel pdfs I have lying around indeed don't list those as NOP either, the block 0F 19-1E are empty in the opcode table A-3. Two-byte Opcode Map: 08H -- 7FH (First Byte is 0FH). A footnote says All blanks in all opcode maps are reserved and must not be used. Do not depend on the operation of undefined or reserved locations.

I also have AMD pdf 24594--Rev. 3.19--September 2012, and that does list the aforementioned block as being NOP in the opcode table A-4. Secondary Opcode Map (Two-byte Opcodes), Low Nibble 8­-Fh. However, the page for the actual NOP instruction only lists 0F 1F.