I'm trying to consolidate some build information by using a common makefile. My problem is that I want to use that makefile from different subdirectory levels, which makes the working directory value (pwd
) unpredictable. For example:
# Makefile.common TOP := $(shell pwd) COMPONENT_DIR := $(TOP)/component COMPONENT_INC := $(COMPONENT_DIR)/include COMPONENT_LIB := $(COMPONENT_DIR)/libcomponent.a
If I include Makefile.common
from a subdirectory, like so, the $(TOP)
directory is incorrect and everything else follows suit:
# other_component/Makefile include ../Makefile.common # $(COMPONENT_LIB) is incorrectly other_component/component
What's the best way to get Makefile.common
to use its own directory path instead of the more fickle pwd
?
The makefile is a text file that contains the recipe for building your program. It usually resides in the same directory as the sources, and it is usually called Makefile .
You can use the -C flag to specify the path to your makefile. This way you can execute it from a different directory. The -f flag has a different use. With that flag you can execute a makefile with a name other than makefile .
Yes, a Makefile can have a directory as target. Your problem could be that the cd doesn't do what you want: it does cd and the git clone is carried out in the original directory (the one you cd ed from, not the one you cd ed to). This is because for every command in the Makefile an extra shell is created.
Expanded assignment = defines a recursively-expanded variable. := defines a simply-expanded variable.
You should be able to use the MAKEFILE_LIST variable, like this:
# This must be the first line in Makefile.common TOP := $(dir $(firstword $(MAKEFILE_LIST)))
From the documentation:
As make reads various makefiles, including any obtained from the MAKEFILES variable, the command line, the default files, or from include directives, their names will be automatically appended to the MAKEFILE_LIST variable. They are added right before make begins to parse them. This means that if the first thing a makefile does is examine the last word in this variable, it will be the name of the current makefile. Once the current makefile has used include, however, the last word will be the just-included makefile.
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