I'm trying to assign the output of this command ( that is in my makefile ) to the makefile HEADER var like in this following line of code:
HEADER = $(shell for file in `find . -name *.h`;do echo $file; done)
The problem is that if I print HEADER in my makefile using:
print: @echo $(HEADER)
I get
ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile ile
And if I run this command directly in the console, and directly where my makefile is:
myaccount$ for file in `find . -name *.h`;do echo $file; done ./engine/helper/crypto/tomcrypt/headers/._tomcrypt_pk.h ./engine/helper/crypto/tomcrypt/headers/tomcrypt.h ./engine/helper/crypto/tomcrypt/headers/tomcrypt_argchk.h ./engine/helper/crypto/tomcrypt/headers/tomcrypt_cfg.h ./engine/helper/crypto/tomcrypt/headers/tomcrypt_cipher.h ./engine/helper/crypto/tomcrypt/headers/tomcrypt_custom.h ./engine/helper/crypto/tomcrypt/headers/tomcrypt_hash.h ./engine/helper/crypto/tomcrypt/headers/tomcrypt_mac.h ....
So I get all my header files. I'm doing this to avoid manually specifying all my .h files manually in my makefile.
Any ideas ?
So put SHELL := /bin/bash at the top of your makefile, and you should be good to go. See "Target-specific Variable Values" in the documentation for more details. That line can go anywhere in the Makefile, it doesn't have to be immediately before the target.
Expanded assignment = defines a recursively-expanded variable. := defines a simply-expanded variable.
Re: Setting Environment variable in Makefile the "$" character is special to make. To get the shell to see one "$", you must use "$$" in the Makefile. 2.) Environment variables can only be inherited from parent to child processes, not vice versa.
You will need to double-escape the $
character within the shell command:
HEADER = $(shell for file in `find . -name *.h`;do echo $$file; done)
The problem here is that make will try to expand $f
as a variable, and since it doesn't find anything, it simply replaces it with "". That leaves your shell command with nothing but echo ile
, which it faithfully does.
Adding $$
tells make to place a single $
at that position, which results in the shell command looking exactly the way you want it to.
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