Committed Vs Retired instruction

Question

It may be a stupid question but I'm not able to find a clear explanation about these 2 phases of an instruction life. My initial thinking was that they are synonymous but I'm not sure anymore. I start to think that

1. For a load commit and retire happens at the same time
2. For a store the commit happen when the instruction update the registers and the retire happens when the store actually leave the store buffer.

Is this wrong ? Does anyone have 2 clears definitions of those terms ?

Cheers.

Answer 1

These terms have no standard definitions. I have seen them being used to mean different things in different books or processor designs:

• In Intel processors, retirement occurs when the reorder buffer entries occupied by the instruction get deallcoated. Memory stores have one additional stage called commit in which the store is actually performed. That's because Intel processors have store buffers where stores can be marked as retired.¹

• Hennessy and Patterson's book mostly uses the term "commit" in the chapter on out-of-order execution. Even stores get performed in the commit stage. Sometimes it uses the term "retire" but without giving a definition that would distinguish it from commit. However, in Appendix C, stores are performed in the 4th stage, called the memory stage, while register updates are performed in the 5th stage, which is called writeback.

• Some books use the terms "complete" and "commit" where "complete" means "retire" in Intel processors and "commit" means "commit". By the way, Intel also uses the term "complete" in their manual which may mean something other than retire depending on the context.
• Sometimes the term "commit" refers to updating both the register and memory state while the term "retire" refers to deallocating architectural resources.
• Sometimes there are used interchangeably. For example, there are academic proposals for microarchitectures that can dispatch stores out-of-order but without using any store buffers. Stores are performed on retirement from the ROB itself.

The terms might be used to mean other things in other contexts. Generally, you can deduce what they mean from the way they are being used by the author and from the overall context.

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Footnote 1: Intel has a patent on an alternate implementation that allows stores to leave the store buffer out-of-order, which they don't implement it in any of their CPUs.

It would be possible to commit stores out-of-order before retirement if the L1D is equipped with a mechanism to distinguish between the globally visible state and the locally visible state of each valid cache line in the cache. This mechanism would be needed to maintain the visible order of the stores. In this hypothetical design, it's also possible to commit stores speculatively, which would require flushing (some of or all the) locally visible states on mispredictions. A store buffer entry that holds a store could optionally be freed when the store commits even if it did not retire yet.