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Starting with the i386 CPU, Intel processors have exposed control registers to allow the kernel to configure the processor and specify characteristics of the currently executing task/process/thread. According to the Intel Systems Programming Manual (section 2-13), the CR1 control register is "Reserved". That is, the kernel manipulating control register CR1 results in undefined behavior. As the articles indicates, there are also CR2, CR3, CR4 and CR8 control registers, though they are not reserved.
Why is CR1 reserved? It is strange that Intel would introduce a reserved control register, and then start adding non-reserved control registers thereafter rather than simply adding functionality to CR1 as doing so would not cause any backwards compatibility breaks (that's the whole point of keeping it reserved). http://www.pagetable.com/?p=364 speculates that CR1 was kept reserved to have a second register available for architectural configuration, but as the article mentions, CR4 was used instead when the i486 was introduced.
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According to the Intel Systems Programming Manual (section 2-13), the CR1 control register is "Reserved". That is, the kernel manipulating control register CR1 results in undefined behavior. As the articles indicates, there are also CR2, CR3, CR4 and CR8 control registers, though they are not reserved.
CR2: This register contains the Page Fault Linear Address when a page fault occurs. CR3: This register is used when virtual addressing is enabled (paging) and contains the physical address of the page directory, page directory pointer table, or ...
A control register is a processor register which changes or controls the general behavior of a CPU or other digital device. Common tasks performed by control registers include interrupt control, switching the addressing mode, paging control, and coprocessor control.
The physical address of the current page directory is stored in the CPU register CR3, also called the page directory base register (PDBR). Memory management software has the option of using one page directory for all tasks, one page directory for each task, or some combination of the two.
The Intel® 64 and IA-32 Architectures Software Developer’s Manual says CR1 — Reserved. So CR1 is unused and reserved to Intel + AMD for future use. Since it is reserved, accessing CR1 throws an exception:
Attempts to reference CR1, CR5, CR6, CR7, and CR9–CR15 result in undefined opcode (#UD) exceptions.
Why they haven't used CR1 when they have used CR2 is anyone's guess. X86 is irregular and indeed, Intel hasn't said anything. This article Why is there no CR1 – and why are control registers such a mess anyway? has some history but really unless Intel says something official, and they haven't, there is no answer.
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