Why "DIV EDX" in MASM always generates processor exception?

Question

I've got that question on my Computer Architecture Exam on Informatics last semester : "Why 'DIV EDX' in MASM always generates processor exception?"
What is the mechanism which generates exception?

Answer 1

When you do 1-operand division on x86 CPUs, EDX:EAX (64 bit) is divided by the 1st operand (32 bit). The result is stored in EAX (32 bit).

So when you divide by EDX:EAX by EDX, what you essentially get is (EDX * 0x100000000 + EAX) / EDX, which result is always above 0x100000000 and does not fit into the target register or the divisor is zero. In both cases a divide exception occurs.

See also this page (from the Intel developer manuals).

Note that this is not specific to the assembler (MASM), but to the platform in this case.