What is the variable $(MAKE) in a makefile?

Question

I am currently learning how to write makefiles. I've got the following makefile (which was automatically generated for a C-project that should run on an ARM chip), and I'm trying to understand it:

    RM := rm -rf      # All of the sources participating in the build are defined here     -include sources.mk     -include FreeRTOS/Supp_Components/subdir.mk     -include FreeRTOS/MemMang/subdir.mk     -...     -include subdir.mk     -include objects.mk      ifneq ($(MAKECMDGOALS),clean)     ifneq ($(strip $(S_UPPER_DEPS)),)     -include $(S_UPPER_DEPS)     endif     ifneq ($(strip $(C_DEPS)),)     -include $(C_DEPS)     endif     endif      -include ../makefile.defs      # Add inputs and outputs from these tool invocations to the build variables       # All Target     all: FreeRTOS_T02.elf      # Tool invocations     FreeRTOS_T02.elf: $(OBJS) $(USER_OBJS)         @echo 'Building target: $@'         @echo 'Invoking: MCU GCC Linker'         arm-none-eabi-gcc -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-sp-d16 -specs=nosys.specs -specs=nano.specs -T LinkerScript.ld -Wl,-Map=output.map -Wl,--gc-sections -lm -o "FreeRTOS_T02.elf" @"objects.list" $(USER_OBJS) $(LIBS)         @echo 'Finished building target: $@'         @echo ' '         $(MAKE) --no-print-directory post-build      # Other Targets     clean:         -$(RM) *         -@echo ' '      post-build:         -@echo 'Generating binary and Printing size information:'         arm-none-eabi-objcopy -O binary "FreeRTOS_T02.elf" "FreeRTOS_T02.bin"         arm-none-eabi-size "FreeRTOS_T02.elf"         -@echo ' '      .PHONY: all clean dependents     .SECONDARY: post-build      -include ../makefile.targets 

I'm trying to wrap my head around the line $(MAKE) --no-print-directory post-build in the rule for making the .elf file.

I cannot find a definition for the variable $(MAKE), so I assume that it is something built-in. What is this line actually doing?

Answer 1

It's a recursive invocation of make itself, forwarding the -t, -n and -q options. This makes sense: you want the nested make invocations to run with these options as well.

Answer 2

From the docs:

The value of this variable is the file name with which make was invoked

It is useful in cases where to make some target you'd have to call its makefile, but you are doing some sort of dry run with -t (--touch), -n (--just-print), or -q (--question) flags. That behaviour would propagate recursively if ($MAKE) is used.