Consider this Makefile
% cat Makefile main: main.o add.o
which uses cc
instead of g++
to link the object files
% make g++ -Wall -pedantic -std=c++0x -c -o main.o main.cpp g++ -Wall -pedantic -std=c++0x -c -o add.o add.cpp cc main.o add.o -o main main.o:main.cpp:(.text+0x40): undefined reference to `std::cout' ...
How do I tell (GNU) Make to use g++
(which links the C++ libraries) instead of cc
?
A makefile is a set of instructions used by make . They can be instructions that build a program, install some files, or whatever you want make to do. A linker is a program that takes object files as input and combines them into an output executable (or shared library).
GCC uses a separate linker program (called ld.exe ) to perform the linking.
(GNU) Make has built-in rules, which is nice, because it is enough to give dependencies without rules:
main: main.o add.o # no rule, therefore use built-in rule
However the build-in rule in this case uses $(CC)
for linking object files.
% make -p -f/dev/null ... LINK.o = $(CC) $(LDFLAGS) $(TARGET_ARCH) ... LINK.cc = $(CXX) $(CXXFLAGS) $(CPPFLAGS) $(LDFLAGS) $(TARGET_ARCH) ... %: %.o # recipe to execute (built-in): $(LINK.o) $^ $(LOADLIBES) $(LDLIBS) -o $@
To let Make chose the correct linker, it is sufficient to set LINK.o
to LINK.cc
. A minimal Makefile
can therefore look like
% cat Makefile LINK.o = $(LINK.cc) CXXFLAGS=-Wall -pedantic -std=c++0x main: main.o add.o
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