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I have a target inside a makefile:
all: $(TARGETS) I want a variant that differs from all only by the fact that it sets an environment variable. Something like:
all-abc: $(TARGETS) ABC=123 but that doesn't work because the dependencies are processed before the variable is set. I've thought about having another dependency before the real ones that just sets the environment variable but I don't think the environment persists across targets. That is to say that
abc: ABC=123 all-abc: abc $(TARGETS) doesn't work. What I ultimately want to be able to do is
$ make all-abc instead of
$ ABC=123 make Is it possible to set an environment variable like this ?
(GNU Make 3.82)
512
$$ means be interpreted as a $ by the shell. the $(UNZIP_PATH) gets expanded by make before being interpreted by the shell.
The $@ and $< are called automatic variables. The variable $@ represents the name of the target and $< represents the first prerequisite required to create the output file. For example: hello.o: hello.c hello.h gcc -c $< -o $@ Here, hello.o is the output file.
There is one way that the makefile can change a variable that you have overridden. This is to use the override directive, which is a line that looks like this: ' override variable = value ' (see The override Directive).
try this:
all: @#usual rule, if you call `make all-abc`, this will print "123" @echo $(ABC) all-abc: ABC=123 all-abc: all @#what you put here it's going to be executed after the rule `all` If you love us? You can donate to us via Paypal or buy me a coffee so we can maintain and grow! Thank you!
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