VHDL: Code to put a numeric value in a STD_LOGIC_VECTOR variable

Question

I would like to enter a number in a a variable of type STD_LOGIC_VECTOR but I have problems with the compiler.

signal cl_output_ChA :   STD_LOGIC_VECTOR (16-1 downto 0);

cl_ouput_ChA <= 111111111111111;

The compiler give me these two messages:

• The integer value of 111111111111111 is greater than integer'high.
• Type of cl_output_ChA is incompatible with type of 111111111111111.

could anyone give me a proper code line to put in this variable a particular numeric value? Thank you so much.

Answer 1

First of all, the error is because the number as you have written it is treated as an integer.

I take that you mean for the number to be binary? In that case use "".

cl_ouput_ChA <= "111111111111111";

You can also go for hex, x"".

cl_ouput_ChA <= x"ffff";

If you want to assign an integer to an std_logic_vector, then you can do it like this.

library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Numeric_STD.all;

...

cl_ouput_ChA <= std_logic_vector(to_unsigned(12345, ch1_ouput_ChA'length)); -- natural
cl_ouput_ChA <= std_logic_vector(to_signed(12345, ch1_ouput_ChA'length));   -- signed

Where 12345 is the integer (or natural) and 16 is the width.

Answer 2

You could also do the following, which puts a 1 in each bit.

cl_ouput_ChA <= (others => '1');