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What does it mean to do a negation of a bit vector in VHDL? For example if I have 10100111 which is a bit vector called temp and I do something like temp := not temp what will my output be?
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If you really want to negate a vector, you need to use a vector which has certain properties defined for it. Specifically: some notion of numerical value (so you can't use bit_vector or std_logic_vector , which are just collections of bits) some notion of "sign"
Description. The Bit_vector type is an unconstrained vector of elements of the bit type. The size of a particular vector is specified during its declaration (see the example below). The way the vector elements are indexed depends on the defined range and can be either ascending or descending (see range).
The std_logic_vector type is used for arrays of std_logic variables and signals. The basic VHDL logic operations are defined on this type: and , nand , or , nor , xor , xnor . These must be given two arrays of the same size; they do the operation on ecah position and return another array.
The VHDL keyword “std_logic_vector” defines a vector of elements of type std_logic. For example, std_logic_vector(0 to 2) represents a three-element vector of std_logic data type, with the index range extending from 0 to 2.
A bit-wise inversion.
In general in VHDL (LRM 7.2.1): "For the unary operation not defined on one-dimensional array types, the operation is performed on each element of the operand, and the result is an array with the same index range as the operand."
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