TLB structure in intel

Question

I started from Patterson & Hennessy book with basic definitions and then followed the intel programming reference documents for more information about TLB.

From the intel documents i got to know the high level design of TLB. such as line size, associativity and levels of caching. But in need a detailed explanation of how TLB caching works with respect to cache misses and its replacement mechanisms in modern CPU. What pages moves
to L2 TLB from L1 TLB ? how many pages can a single entry in TLB address? How many entries are present in TLB ? (In particular DTLB)

Any Information or references will be of great help to me. (If this is not the proper forum for this question, please suggest the right one)

Thank you.

Answer 1

TLB can be called a translation cache and thus, its functioning is almost as that of on-chip caches, e.g., the tradeoffs of exclusive/inclusive hierarchy, multi/single-level, private/shared are same as that in cache. Same for associativity, page size, etc.

One TLB entry only maps one virtual page to physical page, but the page size can be varied, e.g., instead of 4kB, a processor can use 2MB or 2GB, which is called a superpage or hugepage. Or a processor can use multiple page sizes.

Since you are asking for reference, see my survey paper on TLB which answers all these questions and reviews 85+ papers. Specifically, section 2 of the paper references papers that discuss TLB designs in commercial processors.