Ripple carry counter in Verilog with 4 modules and x output

Question

I have tried to implement a ripplecarrycounter in Verilog.

Modules for: dff, tff, ripplecarrycounter, testbench.

My output is incorrectly coming out as "x". Where have I gone wrong?

  `timescale 1ns/1ns
module ripplecounterdataflow(q,clk,clear);
 input clk,clear;
 output [3:0]q;
 tffdataflow t0(q[0],clk,clear);
 tffdataflow t1(q[1],q[0],clear);
 tffdataflow t2(q[2],q[1],clear);
 tffdataflow t3(q[3],q[2],clear);
endmodule

  `timescale 1ns/1ns
module tffdataflow(q,clk,clear);
input clk,clear;
output q;

dffdataflow d0(q,,~q,clk,clear);
 endmodule



  `timescale 1ns/1ns
module dffdataflow(q,qbar,d,clk,clear);
input d,clk,clear;
output q,qbar;
wire s,sbar,r,rbar,cbar;

assign clk=~clk;
assign s=~(sbar&cbar&(~clk));
assign sbar=~(s&rbar);
assign r=~(s&rbar&(~clk));
assign rbar=~(r&cbar&d);
assign cbar=~clear;
assign q=~(s&qbar);
assign qbar=~(cbar&r&q);

endmodule



 `timescale 1ns/1ns
  module testripplecarrycounterdataflow;
   reg clk,clear;
   wire [3:0]q;
 ripplecounterdataflow r0(q,clk,clear); 
  initial 
  begin
  clk=1'b0;
  forever #10 clk=~clk;
 end
  initial
  begin
   #10 clear=1'b0;
   #30 clear=1'b1;
  end
  initial
  begin
  #600 $finish;
 end
  initial
 $monitor($time," q=%b ,clk=%b, clear=%b",q,clk,clear);
 endmodule

Answer 1

You should not assign a value to an input inside a module. In dffdataflow, delete this line:

assign clk=~clk;