For those who do not know, Intel (macro) instructions such as XADD, ADD etc are broken down in to a series of micro-operations (uops), where one macro instruction can have several micro-operations.
I am aware of the Intel developer guides, but they do not seem to detail anything about uops, just the x86 instruction reference.
Is anybody aware of available material referring specifically to the various uops?
You can find detailed information on the number of μops and the ports they can use for most x86 instructions on recent Intel CPUs (from Nehalem to Coffee Lake) on our website uops.info. The website also contains information on the latency and throughput of each instruction. The data was obtained by running automatically generated microbenchmarks both on the actual hardware (using hardware performance counters) and on top of different versions of Intel IACA.
I think Agner Fog's Instruction Tables manual might be what you are seeking; it contains "Lists of instruction latencies, throughputs and micro-operation breakdowns for Intel, AMD and VIA CPUs."
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