Makefile syntax: what is $(RM)?

Question

I saw the following Makefile online (here):

hello:

clean:
    $(RM) hello

When there is a hello.c file in the same directory with the Makefile, make command in Terminal builds hello executable. When make clean is run, hello executable is removed by rm -f hello instead. So, $(RM) hello means rm -f hello here.

• What does $(FOO) mean? Is it a special syntax of Makefile, or something bash command?
• Can I run other commands as well as $(RM), like $(PWD)?

Answer 1

It's a Makefile variable. There are explicit variables (which are defined inside a Makefile) and implicit variables (defined by make, can be overriden by you).

You can see a list of implicit variables with this flag:

make -p

some of the most common variables can be found at: 10.3 Variables Used by Implicit Rules

You can expand a variable with the syntax $(NAME) or ${NAME}