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Make's implicit rules are supposedly there to make writing Makefiles easier but, if my understanding is correct, if my C files depend on any header files, I need to write the rule, explicitly. Am I right? This seems to serioiusly lower the usefulness of implicit rules, since most C files depend on a couple of header files, so I thought perhaps there's something I'm missing.
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Implicit rules tell make how to use customary techniques so that you do not have to specify them in detail when you want to use them. For example, there is an implicit rule for C compilation. File names determine which implicit rules are run. For example, C compilation typically takes a . c file and makes a .o file.
The file name of the target of the rule. If the target is an archive member, then ' $@ ' is the name of the archive file. In a pattern rule that has multiple targets (see Introduction to Pattern Rules), ' $@ ' is the name of whichever target caused the rule's recipe to be run.
A rule appears in the makefile and says when and how to remake certain files, called the rule's targets (most often only one per rule). It lists the other files that are the prerequisites of the target, and the recipe to use to create or update the target.
The include directive tells make to suspend reading the current makefile and read one or more other makefiles before continuing. The directive is a line in the makefile that looks like this: include filenames … filenames can contain shell file name patterns.
You can autogenerate header dependencies with gcc using the following makefile snippet
SOURCES := $(wildcard *.c)
DEPS := $(SOURCES:%.c=%.d)
CFLAGS += -MMD
-include $(DEPS)
The code might need some adjustments to work with your particular ruleset.
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You don't need to write the rule, only the dependencies. Example:
foo.o : foo.h bar.h
The file foo.o will still be generated by the implicit rule, but have the additional dependencies foo.h and bar.h. This dependency line can also be auto-generated by most compilers.
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