make - define multiple variables in the same eval call

Question

I would like to use make's eval function to define several (dynamically-named) variables inside a foreach, but I can't get eval to do this job.

I tried something like this:

$(eval \
    var1 = val1 \
    var2 = val2 \
)

It doesn't work: var1 gets defined as val1 var2 = val2 and var2 is not defined. It makes sense, because I put \ at the end of the second line. But if I remove it, the eval call will never be terminated.

I tried different things to have this \ only seen by eval, but nothing did the trick. Hence the question: is it possible to define multiple variables in the same eval call ?

Of course I could call eval twice... it's rather curiosity.

Answer 1

What separates each variable definition is the newline character, which you are escaping with the backslash. Since you cannot put it directly in the eval function, you have to define it and to use it into eval like this :

define newline


endef

Then if you place the following lines inside a target :

$(eval FOO=abc$(newline)BAR=def)
@echo FOO : $(FOO) BAR : $(BAR)

You will have this result :

FOO : abc BAR : def

Note that if you want to use a variable in the definition of the second one you have to escape the $ character like this :

$(eval FOO=abc$(newline)BAR=def$$(FOO))
@echo FOO : $(FOO) BAR : $(BAR)

The result will eventually be :

FOO : abc BAR : defabc

This is due to the fact that there is a first level of interpretation before that eval actually begins to do its work (the newline is added here) but we want the interpretation of the variable to occur only during the real eval work, when the variable is defined, which is why we need a double $ symbol.

Answer 2

Simply use the foreach:

oneline = FOO=abc BAR=def XX=...
$(foreach line,$(oneline),$(eval $(line)))
$(info $(FOO) $(BAR))

The result:

abc def