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New posts in x86

x86 Program Counter abstracted from microarchitecture?

x86 cpu-architecture riscv instruction-set program-counter

Is it possible to vectorize myNum += a[b[i]] * c[i]; on x86_64?

x86 x86-64 sse simd vectorization

About setjmp/longjmp

c linux x86 setjmp

Porting compiler from x86 Assembly to LLVM

c++ assembly compiler-construction x86 llvm

What's the difference between __popcnt() and _mm_popcnt_u32()?

x86 sse intrinsics sse4

What's inside the stack?

c x86 stack low-level

What is the overhead of using Intel Last Branch Record?

x86 intel trace branch-prediction intel-pmu

Do the x86 virtualization instruction sets (VT-x, AMD-V) have alternate uses?

virtualization x86

Is vxorps-zeroing on AMD Jaguar/Bulldozer/Zen faster with xmm registers than ymm?

assembly x86 avx micro-optimization amd-processor

what's the difference between _mm256_lddqu_si256 and _mm256_loadu_si256

x86 simd intrinsics avx micro-optimization

Two very similar functions involving sin() exhibit vastly different performance -- why?

c performance gcc floating-point x86

L1 memory bandwidth: 50% drop in efficiency using addresses which differ by 4096+64 bytes

c caching memory x86 avx

is there an inverse instruction to the movemask instruction in intel avx2?

x86 intrinsics avx avx2 icc

Is integer overflow undefined in inline x86 assembly?

c gcc x86 undefined-behavior

128-bit values - From XMM registers to General Purpose

assembly x86 sse

Why does DOS set the SP register to 0xFFFE after loading a .COM file?

assembly x86 dos x86-16 callstack

Concrete example of incorrect behavior of an early-clobber affecting a memory operand's addressing mode in GCC inline asm?

assembly gcc x86 inline-assembly register-allocation

Is it possible to use 32 bits registers/instructions in real mode?

assembly x86 operating-system real-mode

Slow jmp-instruction

assembly x86 intel cpu-architecture branch-prediction

Why does cmp 0x84,0x30 trigger the overflow flag?

assembly x86 eflags signed-overflow
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