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New posts in x86

Printing characters to screen ASM in protected mode

assembly x86 nasm vga bochs

Which is the first CPU that Intel has added conditional move instructions to?

x86 instruction-set

How do you print a newline character in BIOS-level assembly?

assembly x86 interrupt bios osdev

What does lea 0x4(%esp),%ecx mean in AT&T syntax?

assembly x86 att

Mixing SSE with AVX128 for shorter instructions?

assembly x86 sse avx micro-optimization

SSE Instruction to load Bytes with Zero Extension?

c assembly x86 x86-64 sse

What exactly does the granularity bit of a GDT change about addressing memory?

assembly x86 protected-mode addressing gdt

Store __m256i to integer

c x86 simd intrinsics avx2

What is "Code" in Linux Kernel crash messages?

linux linux-kernel x86 crash

Compiler choice of not using REP MOVSB instruction for a byte array move

c++ assembly visual-c++ x86 compiler-optimization

Why do call and jump instruction use a displacement relative to the next instruction, not current?

assembly x86 intel machine-code relative-addressing

Can I tell the compiler that I need to earlyclobber a memory operand?

c assembly gcc x86 inline-assembly

What constitutes a read or write to memory/cache in x86 assembly, according to valgrind?

assembly x86 valgrind pascal cpu-cache

What is the meaning of IB read, IB write, OB read and OB write. They came as output of Intel® PCM while monitoring PCIe bandwidth

x86 performance-testing intel intel-pmu mellanox

Benchmarking C struct comparsion: XOR vs ==

c performance x86 comparison benchmarking

How does the CPU decode variable length instructions correctly?

assembly x86 decode instructions

Is it possible to atomically load and store on X86 processors?

c++ concurrency x86 atomic processor

Difference between "mov eax, [num]" and "mov eax, num"

assembly x86 nasm 32-bit

Handling x86 IRQs from secondary PIC: EOI order important?

assembly x86 port irq
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