Logo Questions Linux Laravel Mysql Ubuntu Git Menu
HTML CSS JAVASCRIPT SQL PYTHON PHP BOOTSTRAP JAVA JQUERY R React Kotlin
 

New posts in cpu-architecture

Why doesn't Ice Lake have MOVDIRx like tremont? Do they already have better ones?

assembly x86 intel cpu-architecture instruction-set

Assembly why is "lea eax, [eax + eax*const]; shl eax, eax, const;" combined faster than "imul eax, eax, const" according to gcc -O2?

c assembly optimization x86-64 cpu-architecture

Why is my C++ app faster than my C app (using the same library) on a Core i7

c++ c hardware cpu cpu-architecture

How does the branch predictor know if it is not correct?

assembly cpu cpu-architecture branch-prediction

Using System.getProperty("os.arch") to check if it is armeabi cpu

android cpu-architecture

ARM Cortex-M exception entry and stack framing

exception-handling arm cpu-architecture cortex-m

LFENCE is really useless vs. Spectre #2?

assembly memory x86 x86-64 cpu-architecture

What are function epilogues and prologues?

assembly compiler-construction terminology cpu-architecture calling-convention

Advantages of a 64 bit system

c++ performance architecture 64-bit cpu-architecture

Lightweight method to use Amd64 instructions under 32-bit Windows?

cpu-architecture win32-process x86-64

How does 32-bit address 4GB if 2³² bits = 4 Billion bits not Bytes?

cpu-architecture memory-address addressing

x86-64 usage of LFENCE

assembly x86-64 cpu-architecture atomic

Who Decides Between I/O Mapped and Memory Mapped I/O (x86)

assembly x86 cpu-architecture

Why are there so many CPU architectures: x86, x64, x87, etc...?

cpu-architecture

Is there any architecture that uses the same register space for scalar integer and floating point operations?

cpu-architecture cpu-registers

P6 Architecture - Register renaming aside, does the limited user registers result in more ops spent spilling/loading?

assembly x86 x86-64 cpu-architecture compiler-theory

Software initialization code at 0xFFFFFFF0H

x86 operating-system cpu-architecture boot bios

Is CPU speed limited by the speed of fetching instructions from memory?

performance memory cpu cpu-architecture

superscalar and VLIW

cross-platform parallel-processing cpu-architecture vliw

How do I determine the architecture of an executable binary on Windows 10

windows cpu-architecture portable-executable identification
« Newer Entries Older Entries »