I'd like to define a GNU make pattern rule with the dependencies in a pattern-dependent variable. What I'd like is something like this:
%.exe : $(%_EXE_SOURCES) $(%_EXE_RESOURCES)
$(CSC_V)$(CSC) $(CSCFLAGS) $($*_EXE_CSCFLAGS) -target:exe \
-out:$@ $($*_EXE_SOURCES) $($*_EXE_RESOURCES)
And to later define something like
FOO_EXE_SOURCES = src/Foo.cs
all: Foo.exe
The rule presented works to build; in the body of the rule the $($*_EXE_SOURCES)
variable is expanded to $(FOO_EXE_SOURCES)
, which expands to src/Foo.cs
. The dependencies don't expand properly, however; changing src/Foo.cs does not cause Foo.exe to be rebuilt.
I suspect that this can't actually be done in make, but perhaps someone has a work-alike make fragment?
You could use "secondary expansion". Something like this should accomplish what you are looking for:
Foo_EXE_SOURCES := foo.cs bar.cs baz.cs
all: Foo.exe
.SECONDEXPANSION:
%.exe: $$($$*_EXE_SOURCES)
$(CSC_V)$(CSC) $(CSCFLAGS) $($*_EXE_CSCFLAGS) -target:exe \
-out:$@ $($*_EXE_SOURCES) $($*_EXE_RESOURCES)
Enabling secondary expansion allows the use of automatic variables (i.e. $*
in this case) in the prerequesites list, which is something that would otherwise not work.
If you love us? You can donate to us via Paypal or buy me a coffee so we can maintain and grow! Thank you!
Donate Us With