How to set only the overflow flag ARM assembly?

Question

I have been messing around with the Flags while learning ARM assembly on my Raspberry PI. I have devised of ways only to set the zero flag, only the negative, and only the carry flag. However I can't think of a way to set only the overflow flag. Is it possible? Any help would be appreciated!

The challenge is not to write to the cpsr (as I am not allowed to for various reasons, otherwise that would be the best solution, because it is the best solution)

Edit: only setting the overflow flag with all the others zero/clear. Using only arithmetic or shifting. NZCV = 0001

Edit2: To clarify further, I would think multiple instructions would be needed to achieve this.

Answer 1

I don't see an obvious way with just one instruction, but you could do with combination. For example:

mov  r0, #0x80000000
mov  r1, #0x00000001
subs r2, r0, r1  ; C and V set
mov  r3, #0x10
asrs r3, #1      ; C cleared, V not changed

Answer 2

abc cr
000 00 
001 01  x
010 01 
011 10 
100 01 
101 10 
110 10  x
111 11 

signed overflow is when carry out is not equal to carry in. if the first columns are msbits of operand a b and carry in to the msbit (other bits dont matter for signed nor unsigned overflow), the right colums are carry out and result. If the result is 1 then you get the N bit. so it has to be with the msbits of the operands being 1 and the carry in being a 0

0xxx (carrys)
1xxx (operand a)
1xxx (operand b)

0x80 + 0x80 = 0x00 (zero flag)
0x81 + 0x81 = 0x02 (need some other ones)

  100000010
   10000001
+  10000001
============
   00000010

-127 + -127 = -254 the largest negative you can get is -128, 0x80, so this is a signed overflow.

but there is a carry out isnt there.

So maybe a subtract will work -127 - 127

  100000011
   10000001
+  10000000
============
   00000010

but being a subtract does it invert the carry out to a borrow leaving a 0 in the carry bit? That is not how ARM works, other processors/cores will do this.

So in order to be able to do this you need a processor that defines the carry out as a borrow for a subtract (inverts the carry out at the end of the addition)

You edited your question while writing this, how would a shift operation modify a signed overflow? Needs to be add or subtract (needs to use an adder)