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i know it uses physical address = segment register << 4 + offset register. Although these two registers are 16-bits, how can 8086 handle a 20-bit plus operation?
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To generate the 20-bit address, the CPU shifts the segment 4 bits (1 hex digit) to the left and adds the offset to it. A common combination for segment and offset is the CS and IP registers: together they indicate the address of the next instruction.
Each Segment has a corresponding 16-bit Segment Register which holds the Base Address (starting Address) of the Segment. At any given time, 8086 can address 16-bit x 64KB = 256 KB of memory chunk out of 1MB. 8086 has 20bit address line. So the maximum value of address that can be addressed by 8086 is 2^20 = 1MB.
First, we shift the first address by four bits to the left: 7 2 3 A 0 which is called the base. Then, we add the the second address: 0 0 0 5 which is called the offset. The result of this operation is a new 20-bit address: 7 2 3 A 5 .
Step 1: calculate the length of the address in bits (n bits) Step 2: calculate the number of memory locations 2^n(bits) Step 3: take the number of memory locations and multiply it by the Byte size of the memory cells.
The Bus Interface Unit consists of segment registers, adder to generate 20 bit address and instruction prefetch queue. Once this address is sent out of BIU, the instruction and data bytes are fetched from memory and they fill a First In First Out 6 byte queue.
See a document called "8086_Internal_Block_diagram_enotes.pdf", easily to be found via Google. Also see this document, the section about the Bus Interface Unit.
So the processor generates these 20-bit addresses "on demand" with a dedicated internal 20-bit register, if you will.
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