I'm generating the following instruction for 64 bit x86:
41 F3 0F 10 46 10 movss XMM0,014h[R14]
Unfortunately, it seg faults on that line. gdb disassembles it as:
0x0000000000402054 <+320>: rex.B
0x0000000000402055 <+321>: movss 0x14(%rsi),%xmm0
Note that the rex.B override is not recognized, and the index is RSI instead of R14.
Is the instruction invalid? I can't find any indication that this encoding is invalid in the AMD 64 bit instruction reference.
objdump also fails to recognize it as a valid instruction:
41 rex.B
f3 0f 10 46 10 movss 0x10(%rsi),%xmm0
What's going on here?
Finally, I figured it out. The rex byte goes second for this instruction, as in:
F3 41 0F 10 46 10
If you love us? You can donate to us via Paypal or buy me a coffee so we can maintain and grow! Thank you!
Donate Us With