Can I regenerate a makefile for a C project, with correct link order and dependencies?

Question

I have source code I last worked on in the late 90's-2000 and have it all backed up, apart from the makefile (yes berate away, bad backups are almost as good as no backups): so... I am wondering if there is any automated way to generate the makefile or a good way to analyse the dependencies quickly?

Specifically I am looking for:

• a tool which could analyse the dependencies and correct the link order for me.
• if such does not exist, then advice is greatly appreciated as to how to best approach this problem from someone who has had similar problem(s) in the past
• failing either of the above two options, I think the best approach is to create an analysis/make-file creation tool which can automatically generate the dependencies order for linking (I have held off on this approach as time is always in short supply to squeeze in another project).

The reason for this quest for help/advice is that the code-base is 300,000 lines of code (excluding comments) and spans hundreds of C/O files, and as often as I have tried creating a make-file by hand, it frustrates and confounds, hence my last attempt to seek help and ask in here.

For reference: I have tried Cmake, AutoMake, GenMake and similar tools in the past to generate the makefile, all to no avail, as the dependencies are horrendous.

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Generic makefile script

As it may be of use to others, here is the makefile I usually use for less convoluted C and C++ projects, as it saves me having to worry about creating a new one every time:

$(VERBOSE).SILENT:
PROGRAMNAME = prog
CC = gcc
CC += -c
CPP = g++
CPP += -c
ASM = nasm
ASM += -f elf -d ELF_TYPE
LD = g++
OBJFILES = $(patsubst %.c,%.o,$(wildcard *.c))
OBJFILES += $(patsubst %.s,%.o,$(wildcard *.s))
OBJFILES += $(patsubst %.cpp,%.o,$(wildcard *.cpp))

all: $(PROGRAMNAME)

clean:
    @echo "Cleaning object files"
    @echo "    rm -f     *.o"
    rm -f *.o
    @echo "Cleaning backups"
    @echo "    rm -f     *~"
    rm -f *~
    @echo "Removing program file"
    @echo "    rm -f     "$(PROGRAMNAME)
    rm -f $(PROGRAMNAME)

%.o: %.s
    @echo "Assembling ASMs "$@
    @echo "    ASM       "$<
    $(ASM) $<

%.o: %.c
    @echo "(C)ompiling "$@
    @echo "    CC        "$<
    $(CC) $<

%.o: %.cpp
    @echo "(C++)ompiling "$@
    @echo "    CPP       "$<
    $(CPP) $<

$(PROGRAMNAME): $(OBJFILES)
    @echo "Get ready...."
    @echo "Linking "$@
    @echo "    LD        -o "$(PROGRAMNAME)"        "$(OBJFILES)
    $(LD) -o $(PROGRAMNAME) $(OBJFILES)
    @echo "Cry if it worked! Scream swear and cry if it did not..."

strip: $(PROGRAMNAME)
    @echo "Stripping "$(PROGRAMNAME)
    echo -n "Size of "$(PROGRAMNAME)" before stripping is "
    ls -sh $(PROGRAMNAME) | cut -d' ' -f1
    @echo "    Stripping     "$(PROGRAMNAME)
    strip $(PROGRAMNAME)
    echo -n "Size of "$(PROGRAMNAME)" after stripping is "
    ls -sh $(PROGRAMNAME) | cut -d' ' -f1

nothing:
    @echo "Nothing to do; see you later - I'm going home!!!"
    @echo "Hey, try some of these:"
    @echo "make all   - this would be the one you want"
    @echo "make strip - does not work in the real world, only in computers"
    @echo "make clean - will help clean your mind up"

Answer 1

You are looking for the classic Unix tool from MIT, makedepend.

Answer 2

gcc & clang can generate dependencies, see Advanced Auto-Dependency Generation , this won't solve the whole problem but shall help you.