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I'm an FPGA noob trying to learn Verilog. How can I "assign" a value to a reg in an always block, either as an initial value, or as a constant. I'm trying to do something like this in the code below. I get an error because the 8 bit constant doesn't count as input. I also don't want to trigger the always off of a clock. I just want to assign a register to a specific value. As I want it to be synthesisable I can't use an initial block. Thanks a lot.
module top ( input wire clk, output wire [7:0] led ); reg [7:0] data_reg ; always @* begin data_reg = 8'b10101011; end assign led = data_reg; endmodule 
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It is illegal to drive or assign reg type variables with an assign statement. This is because a reg variable is capable of storing data and does not require to be driven continuously. reg signals can only be driven in procedural blocks like initial and always .
An initial block is not synthesizable and hence cannot be converted into a hardware schematic with digital elements. Hence initial blocks do not serve much purpose than to be used in simulations. These blocks are primarily used to initialize variables and drive design ports with specific values.
The value can either be a constant or an expression comprising of a group of signals. The assignment syntax starts with the keyword assign, followed by the signal name, which can be either a signal or a combination of different signal nets.
reg is by default a one bit unsigned value.
You can combine the register declaration with initialization.
reg [7:0] data_reg = 8'b10101011; Or you can use an initial block
reg [7:0] data_reg; initial data_reg = 8'b10101011; If you love us? You can donate to us via Paypal or buy me a coffee so we can maintain and grow! Thank you!
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