armv8 - AArch64 vs AArch32 Stack Pointer Register?

Question

Background: On AArch32, every mode (FIQ, IRQ etc) has a "banked" copy of the SP (R13) register. This allowed for different modes to maintain their own separate stack.

Now on AArch64 this does not seem to be the case. For example: If we consider EL1, on AArch64 the two modes equivalent to a IRQ and SVC are EL1’h’ and EL1’t’ (h = handler and t = thread). In this case, would both the ‘h’ and ‘t’ modes have to share a common stack ? I ask because there is only one Stack Pointer per EL, namely SP_ELx.

Questions:

• How does AArch64 manage this difference for an OS like Linux. Would two modes like EL1’h’ and EL1’t’, share the same stack ?
• Similar to AArch32, where Linux has different stacks for IRQ and SVC modes, what would one have to do to maintain different stacks for EL1'h' and EL1't', in case of AArch64 ?

Answer 1

First of all we need to separate ARMv7/ARMv8 (architecture versions) from AArch32/AArch64 execution states (32-bit vs. 64-bit).

Where an ARMv8 processor provides AArch32 execution state at EL1 (kernel), that has the same exception model as in ARMv7. When EL1 is in AArch64 execution state, it uses a completely different exception handling model.

AArch64 EL1 does not have IRQ and SVC or the other modes that AArch32 does - this is why it needs/has only one exception stack.