x86 PIC, is it correct for QEMU to raise interrupts on all CPUs?

Question

I recently had to work around a proprietary OS issue with the x86 PIC where the OS expected timer interrupts ONLY on CPU0. I enabled the IO-APIC to get around this and did CPU steering so the interrupts went only to CPU0. Problem solved.

I was told that our hardware is broken to do such a thing. i.e. raise timer interrupts on all CPUs when only a PIC is in use. The 'hardware' in question is QEMU/KVM.

Is QEMU/KVM at fault here ? Is the OS making an invalid assumption ?

My suspicion is that QEMU/KVM is perfectly correct in doing this and the OS should be able to handle timer interrupts on CPU != 0...

Answer 1

I think it's true, the PIC ordinarily delivers interrupts only to CPU 0, including timer interrupts. Most OSes will not attempt SMP with PIC, since the CPU1-whatever cannot get or receive any interrupts (including some kind of timer interrupt for process scheduling); for example, Linux with "noapic" disables all but CPU0. I think this OS hit an odd corner case in qemu.