I am reading the Intel x86_64 guide vol.1 to refresh how memory addressing works.
Still,
3.7.5 Specifying an Offset
The offset part of a memory address can be specified directly as a static value (called a displacement) or through an address computation made up of one or more of the following components:
• Displacement — An 8-, 16-, or 32-bit value.
I read in Agner Fog's assembly guide that 64-bit absolute addressing was possible when used with (r/e)ax register.
So..
Is it possible, or not, to use absolute addressing with 64 bits addresses to jmp, mov and call (with all the registers), or will I have to keep using the Base + displacement combo?
Note that mov absolute_addr64, %rax
is only available with rax
as the target.mov $imm64, %reg
is available for any register.
See Load from a 64-bit address into other register than rax, and why we can't move a 64-bit immediate value to memory?
When AMD designed the AMD64 architecture, they basically said 2GB of code should be enough for everyone. (Per executable and per shared library; calls between things that aren't statically linked together typically need indirection through a full 64-bit address anyway.)
https://gitlab.com/x86-psABIs/x86-64-ABI describes the small, medium, and large code models for the x86-64 System V ABI (used on everything non-Windows.)
small: normal 32bit relative displacements for every jump, call, and memory displacement. (All symbols are known to be located between 0
and 2^31 - 2^24 - 1
).
medium: small code, but the data section is split into two parts: regular and large (.ldata
, lrodata
, .lbss
).
This model requires the compiler to use
movabs
instructions to access large static data and to load addresses into registers, but keeps the advantages of the small code model for manipulation of addresses in the small data and text sections (specially needed for branches)By default only data larger than 65535 bytes will be placed in the large data section
The compiler is required to use the
movabs
instruction, as in the medium code model, even for dealing with addresses inside the text section. Additionally, indirect branches are needed when branching to addresses whose offset from the current instruction pointer is unknown.It is possible to avoid the limitation on the text section in the small and medium models by breaking up the program into multiple shared libraries, so this model is strictly only required if the text of a single function becomes larger than what the medium model allows.
Medium PIC needs to movabs / lea / add
to generate RIP-relative addresses with larger than 32bit displacements.
Large PIC needs that for addressing the global offset table and procedure linkage table, too.
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