Why isn't parameter being passed properly in Verilog?

Question

I have two verlog modules as seen below. The parameter statement is supposed too allow me to pass the bus width i'd like to instantiate another module at.

I keep getting an error when trying to compile saying "Port expression 64 does not match expected width 1 or 2."

module LabL3;
parameter SIZE = 64;
reg [SIZE-1:0]a;
reg [SIZE-1:0]b;
reg c;
wire [SIZE-1:0]z;
integer i,j,k;
yMux #(SIZE) mux(z,a,b,c);

initial 
    begin
    for(i=0;i<4;i=i+1)begin
        for(j=0;j<4;j=j+1)begin
            for(k=0;k<2;k=k+1)begin
    a=i;b=j;c=k;
    #1$display("a=%d b=%d c=%d z=%d",a,b,c,z);
            end
        end
    end
    end
endmodule

and the other file is:

module yMux(z,a,b,c);
parameter SIZE= 0;
output [SIZE-1:0]z;
input [SIZE-1:0]a,b;
input c;
yMux1 mux[SIZE-1:0](z,a,b,c);
endmodule

and lastly

module yMux1(z,a,b,c);
output z;
input a,b,c;
wire not_C, upper, lower;

not my_not(notC,c);
and upperAnd(upper,a,notC);
and lowerAnd(lower,c,b);
or my_or(z,upper,lower);

endmodule

and the command I am using is: iverilog LabL3.v yMux1.v yMux.v

I have tried the different syntax's for parameter passing. All give the same result. Any hints would greatly be appreciated. - Chris

Answer 1

You are using vectored instances:

yMux1 mux[SIZE-1:0](z,a,b,c);

Where you end up with SIZE number of yMux1 instances. This should connect z,a,b bitwise correctly and connect the single bit c to all yMux1 c ports via replication.

If you really want to drive all c ports to the same value I would try manually replicating the port with:

yMux1 mux[SIZE-1:0](z,a,b,{SIZE{c}});

Example on EDAPlayground looks fine to me. Could be an issue with the specific tool not supporting vectored instances correctly.

---

When possible I would recommend using named port connections (ANSI header style) from section 23.2.1 of the SystemVerilog IEEE 1800-2012 Standard.

This style is very clear as to your design intent, I find it much easier to read which relates to less bugs. It also allows easier refactoring of the code due to the named connections and not being order dependent.

module LabL3;
  parameter SIZE = 64;
  reg  [SIZE-1:0] a;
  reg  [SIZE-1:0] b;
  reg             c;
  wire [SIZE-1:0] z;

  yMux #(
    .SIZE(SIZE)
  ) mux (
    .z(z),
    .a(a),
    .b(b),
    .c(c)
  );

yMux definiton:

module yMux #(
 parameter SIZE= 0
) (
 output [SIZE-1:0] z,
 input  [SIZE-1:0] a,
 input  [SIZE-1:0] b,
 input             c
);
// ...
endmodule

An example of the above code on EDAPlayground.