What memory is used for storing the reset vector?

Question

from wikipedia: The reset vector for the 8086 processor is at address FFFF0h Where is the reset vector stored?

Answer 1

The address of the reset vector — in this case FFFF0h — of a CPU is fixed in hardware by design. It is part of the specification of the CPU. The CPU goes to that address, fetches whatever address it finds there, jumps to that address, and begins executing. It is a kind of double indirection with a fixed first step (the CPU goes to address FFFF0h, which is most likely in a ROM of some kind) and a second step that depends on the machine. In a PC, the vector will point to early initialization code in the BIOS that begins the boot process, but more generally, it could in principle be anything that can be hardware memory-mapped into that address, but 99.9% of the time, it's some kind of ROM (PROM, EPROM, EEPROM, etc.).

For example, suppose that the design specifications for a CPU with a 32-bit address space is such that the cold boot (power on) vector is 0xffff4, the reset vector is 0xffff0, and the intention is that the bottom 1MiB (0x00000 to 0xfffff) is reserved for ROM boot code. Suppose that you buy a board with a socket for a 1MiB ROM that's mapped into that address space.

Then you write a ROM BIOS for this machine that is, say, about half a megabye, and the result of fiddling around with your compiler and assembler is that you end up with an object-code file where the very first code that you want to run on power-on is 0x1230 bytes offset into the file, where you do a little ultra-basic setup, and then jumps to offset 0x3210 in the file, where the code is adequate to start from a warm boot or reset. In this case, you would pad your object-code file out to 1MiB, make sure that the value 0x00003210 is at offset 0x000ffff0, and the value 0x00001230 is at offset 0x000ffff4.

You burn the file onto a compatible ROM starting at address 0x0 so that the file offsets translate directly into addresses in the range 0x00000000 to 0x000fffff. When the machine is turned on, it goes immediately to address 0x000ffff4, finds the value 0x00001230 there, loads that value into the instruction pointer (or program counter, whatever you want to call it) and begins executing at address 0x00001230 where your cold boot code is.

The CPU knows if it has been reset or turned completely off and then on again. If the CPU is reset (e.g. by being triple faulted), then instead of going to address 0x000ffff4, it goes to its reset vector at 0x000ffff0, loads the value 0x00003210 and begins executing that. This is essentially how a PC can skip the POST when it's rebooted, but not when it's powered off and back on again. It has different vectors depending on whether it's “cold” or “warm”.

In reality, modern CPUs almost certainly execute a bunch of microcode internally before going near the address and data buses to fetch the reset or boot vectors. This microcode is quite likely to be uploadable to the CPU, but that doesn't change the basic idea at the architectural level, and “vectoring” like this is a very, very old practice that arises from the ubiquity (on non-vectored CPUs) of the reset address containing instructions equivalent to “jump to address 0x01230”, effectively doing the “vectoring” manually.