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After going through some basics documents what I understood is, Base Address Register is Address space which can be accessed by PCIe IP. PCIe IP can either transmit data in Base Address Register or it can write received data on to it.
Am I right? Or missing anything?
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This is the PCIe Link Status register in the Board Information Registers IP core of the PCI Express Interface Block. This register indicates the PCI Express link status. For additional details of PCIe Link Status Information refer to the Xilinx Ultrascale devices Gen3 Integrated Block for PCI Express IP core.
The base address of the PCIe enhanced configuration address space is set to C400_0000h (3GB+64MB) in the PCIe root complex register. The target PCIe device resides in bus number one (1). The target PCIe device is device number zero (0) in the corresponding bus. The target PCIe function is function number zero (0).
Simple BDF notation BDF stands for the Bus:Device. Function notation used to succinctly describe PCI and PCIe devices. The simple form of the notation is: PCI Bus number in hexadecimal, often padded using a leading zeros to two or four digits.
Each PCIe function is identified by a four-digit. hexadecimal function ID that is unique within a processor configuration. You must specify a function type and a CHID value which describes the related PCIe adapter card in the assigned slot of the I/O drawer.
Linux kernel point of view
A good way to learn something is to interact with it, so let's use the Linux kernel for that.
Here is a minimal PCI example on a QEMU emulated device: https://github.com/cirosantilli/linux-kernel-module-cheat/blob/366b1c1af269f56d6a7e6464f2862ba2bc368062/kernel_module/pci.c
The first 64 bytes of the PCI configuration are standardized as:
Image from LDD3.
So we can see that there are 6 BARs. The wiki page then shows the contents of each BAR:
The region width requires a magic write however: How is a PCI / PCIe BAR size determined?
This memory is setup by the PCI device, and gives information to the kernel.
Each BAR corresponds to an address range that serves as a separate communication channel to the PCI device.
The length of each region is defined by the hardware, and communicated to software via the configuration registers.
Each region also has further hardware defined properties besides length, notably the memory type:
IORESOURCE_IO: must be accessed with inX and outX IORESOURCE_MEM: must be accessed with ioreadX and iowriteX Several Linux kernel PCI functions take the BAR as a parameter to identify which communication channel is to be used, e.g.:
mmio = pci_iomap(pdev, BAR, pci_resource_len(pdev, BAR)); pci_resource_flags(dev, BAR); pci_resource_start(pdev, BAR); pci_resource_end(pdev, BAR); By looking into the QEMU device source code, we see that QEMU devices register those regions with:
memory_region_init_io(&edu->mmio, OBJECT(edu), &edu_mmio_ops, edu, "edu-mmio", 1 << 20); pci_register_bar(pdev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &edu->mmio); and it is clear that properties of the BAR are hardware defined, e.g. the BAR number 0, has type memory PCI_BASE_ADDRESS_SPACE_MEMORY, and the memory region is 1MiB long 1 << 20.
See also: http://wiki.osdev.org/PCI#Base_Address_Registers of course.
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I think this is a very basic question and I would suggest to read:
A Base Address Register (BAR) is used to:
- specify how much memory a device wants to be mapped into main memory, and
- after device enumeration, it holds the (base) address, where the mapped memory block begins.
A device can have up to six 32-bit BARs or combine two BARs to a 64-bit BAR.
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