What is pipelining? how does it increase the speed of execution?

Question

I believe that no question is silly if it is bugging you. I have this question about pipe-lining?

What is pipe-lining?

Theory says that : "With pipelining, the CPU begins executing a second instruction before the first instruction is completed. Pipelining results in faster processing because the CPU does not have to wait for one instruction to complete the machine cycle."

My question is considering i am working on a uni-processor system, where only one instruction can be executed at a time, how is it possible that simultaneous operation of fetching next instruction is performed when my CPU is busy? If i am lacking conceptual clarity please throw some light on me. If there is separate hardware which makes simultaneous processing happen, what is it? Kindly explain.

Answer 1

Pipelining has nothing to do with uni- versus multi-processor systems. It has to do with thinking hard about the steps taken in executing a single instruction on a machine, in hardware.

Imagine you want to implement the MIPS "add-immediate" instruction, addi $d, $s, $t, which adds an integer stored in the register named by $s to an integer $t directly encoded in the instruction, and stores the result in the register named by $t. Think about the steps you'd need to take to do that. Here's one way of breaking it down (for example only, this doesn't necessarily correspond to real hardware):

1. Parse out the (binary-encoded) instruction to find out which instruction it is.
2. Once you recognize that it is an addi instruction, parse out the source and destination registers and the literal integer to add.
3. Read the appropriate register, and compute the sum of its value and the immediate integer.
4. Write the result into the named result register.

Now remember, all this needs to be built in hardware, meaning there are physical circuits associated with each of these things. And if you executed one instruction at a time, three fourths of these circuits would be sitting idle, doing nothing all the time. Pipelining takes advantage of this observation: If the processor needs to execute two addi instructions in a row, then it can:

1. Identify the first one
2. Parse the first one, and identify the second one with circuits that would otherwise be idle
3. Add the first one, and parse the second
4. Write out the first one, and add the second
5. Write out the second one

So now, even though each instruction takes 4 processing rounds, the processor has finished two instructions in just 5 rounds total.

This gets complicated due to the fact that sometimes you've got to wait for one instruction to finish before you know what to do in the next one (or even what the next one is), but that's the basic idea.