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I found these pseudo variable name in my makefile in WDK build environment. What is referenced by these variables? It is a little hard for me to get the answer by search engine because they are special, I believe.
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Inside actions we can use: $@ to represent the full target name of the current target $? returns the dependencies that are newer than the current target $* returns the text that corresponds to % in the target $< returns the name of the first dependency $^ returns the names of all the dependencies with space as the ...
This special significance of ' $ ' is why you must write ' $$ ' to have the effect of a single dollar sign in a file name or recipe. Variable references can be used in any context: targets, prerequisites, recipes, most directives, and new variable values.
the := will set the value once to the variable, ie it wont be re-evaluated everytime make encouters that variable.
Special characters in a makefile In macros, a backslash ( \ ) followed by a newline character is replaced by a space. In commands, a percent symbol ( % ) is a file specifier. To represent % literally in a command, specify a double percent sign ( %% ) in place of a single one.
These are automatic variables:
$@ The file name of the target of the rule. If the target is an archive member, then ‘$@’ is the name of the archive file. In a pattern rule that has multiple targets (see Introduction to Pattern Rules), ‘$@’ is the name of whichever target caused the rule's recipe to be run.
$< The name of the first prerequisite. If the target got its recipe from an implicit rule, this will be the first prerequisite added by the implicit rule (see Implicit Rules).
They are used to build rules that can be applied to different targets so that one does not need to repeat the same rule for each and every file that must be worked on...
PS: To find the answer, I first looked for the 'all documentation on a single page' for GNU make, then used my browser's search function...
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