Vivado: Warning The clock pin x_reg.C is not reached by a timing clock (TIMING-17)

Question

I'm trying to compile some FPGA code using Xilinx's Vivado tool. However, when I run "Synthesis" and then select "Report methodology"...I get the following list of Bad Practices:

TIMING-17
TIMING #1 Warning The clock pin last_anthony_reg.C is not reached by a timing clock 
TIMING #2 Warning The clock pin last_paul_reg.C is not reached by a timing clock 
TIMING #3 Warning The clock pin last_steven_reg.C is not reached by a timing clock 

I'm wondering what is causing this "WARNING" message... I tried looking at the schematic... but it looks ok to me... just see a FDCE and some LUTS, nothing out of the ordinary there.

Here's my VHDL Entity for the FPGA top-level:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity example1 is
    port(
        clk           :in    std_logic;
        clear         :in    std_logic;

        richard       :out   std_logic;
        james         :in    std_logic;
        michael       :in    std_logic;
        william       :out   std_logic;       
        david         :out   std_logic;       
        robert        :in    std_logic
    );
end entity;

And the VHDL architecture:

architecture rtl of example1 is
    signal matthew                :std_logic_vector(1 downto 0);
    signal anthony, last_anthony  :std_logic;
    signal steven,  last_steven   :std_logic;
    signal paul,    last_paul     :std_logic;    
begin

process(clk)
begin
    if (rising_edge(clk)) then
        last_anthony <= anthony;
        last_steven  <= steven;
        last_paul    <= paul;
    end if;
end process;

matthew <= (michael and not last_paul) & (robert and not last_steven);

process(
    clear,
    matthew,
    james,    
    last_anthony,
    last_steven,
    last_paul    
)
begin

    if (clear = '1') then
        anthony  <= '0';
        steven   <= '0';
        paul     <= '1';          
    else
        --defaults

        case matthew is

        when "00" =>
            anthony  <= james;
            steven   <= '1';
            paul     <= '0';

        when "01" =>
            anthony  <= last_anthony;
            steven   <= last_steven;
            paul     <= last_paul;

        when "10" =>
            anthony  <= james;
            steven   <= '1';
            paul     <= '0';

        when "11" =>
            anthony  <= last_anthony;
            steven   <= '0';
            paul     <= '1';

        --synthesis translate_off                
        when others =>
            anthony  <= 'X';
            steven   <= 'X';
            paul     <= 'X';
        --synthesis translate_on

        end case;            
    end if;
end process;

william   <= steven;
david     <= paul;
richard   <= anthony;    

end architecture;

Answer 1

Can't vivado just infer which signal is the clock based on which ever signal is going to "posedge" or "rising_edge" statement?

Vivado knows what all the clocks are (after all it gives you a warning on your clock pin), but it does not know the parameters of that clock: frequency, duty cycle etc. That is what it complains about: the pin is reached by a clock but not a clock which has timing information: a 'timing clock'.

You have to specify those in the constraints file like:

# define ext pll clock as 100 MHz for timing check
create_clock -period 10.000 -name ext_pll_in [get_ports PL_HP66]

I understand there is a 'Constraints wizard' but I have never used it.
You get to the 'Constraints wizard' option after you have run synthesis and then 'open synthesized design'.