Oldfart questions

Oldfart answers

• Difference between 1 and 1'b1 in Verilog
• qt 5.2 serial port write issues with windows 7
• Vivado: Warning The clock pin x_reg.C is not reached by a timing clock (TIMING-17)
• Passing parameters between Verilog modules
• The difference between x and z
• Prefered syntax for verilog module declaration
• Verilog: Naming convention