vhdl: convert vector to string

Question

How can I convert a std_logic vector, bit_vector or any other vector to string?

Signal a,b          : UNSIGNED(7 DOWNTO 0);
SIGNAL x,y,z    : BIT_VECTOR(7 DOWNTO 0);

...

report "value: " & BIT_VECTOR'Image(x) severity note;
report "and this one: " & to_string(a) severity note;

This does not work, so how can I convert a vector to a string?

Answer 1

The VHDL-2008 standard defines to_string for std_logic_vector and std_ulogic_vector, as well as a variety of other types. It might be easiest to use the VHDL-2008 mode (most simulators support 2008 nowadays).