o 2.5+ year of ASIC design experience including HDL coding, design linting and synthesis, Regression and scripting

o Successfully configured GTX for USB3.x using ZYNQZC706

o Having knowledge of SGDMA, AXI,AHB/APB, USB3.0, SSIC, MIPI M-PHY and other custom bus interfaces

o Work done on SGDMA, SSIC, USB3.1 with USB3.0 backward compatibility of Link-Layer (SSIC) etc

o Good hands on Xillinx XST tool and SpyGlass