SIMD vs Vector architectures

Question

What is the difference between SIMD and vector processors? My current understanding is that Vector processing is a subset of SIMD. But I was told that "SIMD is not restricted to vectors" and I don't know exactly what that means. Any concrete examples?

Also, why are scalar architectures preferred to vector architectures? Is it because they are easier to implement and program?

I am aware that we have SISD (regular 1 core CPUs), SIMD (SSE extensions on single/multi core processors), MIMD (errmm.. roughly something like MPI I guess, so clustering!), and MISD (which has been deemed impractical/infeasible). Apart from this, some other things I have read about are Vector processing and Superscalar architectures. Any new architectures that I missed and should know about? Thanks!

Answer 1

Flynn's Taxonomy is a classification of computer architectures. By Flynn's Taxonomy vector processing falls into the class of SIMD. There are architectures which are not vector processors but fall into the SIMD class. Examples are e.g. the Connection Machine and many GPUs where multiple processors execute the same instructions.

MMX, SSE, Altivec, etc fall into vector processing as well as the SIMD class. There are many names referring to the same concept: subword parallelism, small scale SIMD, short vector processing, SIMD within a register (SWAR) or most commonly multimedia extensions.

Traditionally vector processors like the Cray or the STAR have used larger and variable vector sizes.

Superscalar is a way to implement a processor but does not make any statement about its instruction set like Flynn's Taxonomy does.

Answer 2

A practical example could be found from comparison of ARM Neon vs ARM VFP. The first is more classical SIMD evaluating 2,4,8 or 16 items in parallel (or mostly parallel). The other is a floating point extension, that is programmed to sequentially iterate over two sets of successive registers (perhaps allowing a skip by 2) eg. S0..S3, S8..S11 and writing the result to S12..S15.

The latter architecture handles a variable number (1-4) operations with the same instruction using 1-4 clock cycles to complete the task. If the architecture would allow say 128 operations per instruction, the conceptual difference between the systems would be clearer -- even though both would be vector and SIMD architectures.