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I found references to hart on page 35 of the RISC-V 2.1 spec. However, I could not find a definition for hart in this document. Does hart refer to a hardware-thread or something more sinister?
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In simple language, a hart is a RISC-V execution context that contains a full set of RISC-V architectural registers and that executes its program independently from other harts in a RISC-V system.
RISC-V (pronounced "risk-five" where five refers to the number of generations of RISC architecture that were developed at the University of California, Berkeley since 1981) is an open standard instruction set architecture (ISA) based on established RISC principles.
RISC-V (pronounced “risk-five”) is an open, free ISA enabling a new era of processor innovation through open standard collaboration.
Pronounced "risk-five," RISC-V is an ISA based on reduced instruction set computer (RISC) principles. An Instruction Set Architecture (ISA) is part of the abstract model of a computer that defines how the CPU is controlled by the software.
Yes, a hart is a hardware thread.
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A RISC-V compatible core might support multiple RISC-V-compatible hardware threads, or harts, through multithreading.
The RISC-V Instruction Set Manual
Volume I: Unprivileged ISA Document Version 20191214-draft
Page 2
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