RISC-V assembly simulator [closed]

Question

I'm trying to learn the RISC-V ISA. Is there a way to simulate RISC-V assembly code just like in MARS for the MIPS ISA?

Answer 1

It sounds like you're looking for an instruction-level RISC-V simulator with an integrated front end that allows you to interactively edit machine code as well as view and manipulate the CPU state. I don't know of any tool for RISC-V that is as tightly integrated as MARS, but you can achieve a close approximation by combining some existing RISC-V tools, namely:

• An ISA simulator (Spike or QEMU)
• A RISC-V toolchain with assembler and compiler (RISC-V GNU toolchain)
• A debugger (gdb, included in the above toolchain)
• A debugger front end (gdb tui mode, DDD, gdbgui, or others)

I have had luck using QEMU + gdb or gdbgui as follows:

$ qemu-system-riscv32 -S -s -kernel /path/to/myprog.elf -nographic

Then in another console:

$ riscv64-unknown-elf-gdb /path/to/myprog.elf
(gdb) target remote localhost:1234
or
$ gdbgui -r -n -g /path/to/riscv64-unknown-elf-gdb /path/to/myprog.elf

NOTE: I notice that the gdb built under the riscv toolchain does not include support for tui mode by default.

NOTE2: QEMU is actually more than an ISA simulator -- it simulates various specific RISC-V target boards and their attendant peripherals.