Order of register stores in STP

Question

In AArch64 assembly, the following line

stp x25, x30, [sp,#48]

stores x25 at sp+48 and x30 at sp+56, right?

Answer 1

Yes. From this manual, page C6-1237 and following:

Signed offset

[...]

64-bit variant

Applies when opc == 10.

STP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]

Decode for all variants of this encoding

boolean wback = FALSE;
boolean postindex = FALSE;

[...]

Shared decode for all encodings

[...]

integer n = UInt(Rn);
integer t = UInt(Rt);
integer t2 = UInt(Rt2);
[...]
integer scale = 2 + UInt(opc<1>);
integer datasize = 8 << scale;
bits(64) offset = LSL(SignExtend(imm7, 64), scale);

[...]

Operation for all encodings

constant integer dbytes = datasize DIV 8;

[...]

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n];

if !postindex then
    address = address + offset;

[...]
data1 = X[t];
[...]
data2 = X[t2];

Mem[address, dbytes, AccType_NORMAL] = data1;
Mem[address+dbytes, dbytes, AccType_NORMAL] = data2;

Let's go through this, top to bottom. Your stp x25, x30, [sp,#48] is a 64-bit signed-offset stp, which decodes as:

n = 31
t = 25
t2 = 30
scale = 3 // since opc = 0b10
datasize = 64
offset = 48

Plug that into the operation pseudocode, substitute variables for their values, and you effectively get:

CheckSPAlignment();
Mem[SP[] + 48, 8, AccType_NORMAL] = X[25];
Mem[SP[] + 56, 8, AccType_NORMAL] = X[30];