I have the following files:
Child.c , Cookie.c , Cookie.h , CookieMonster.c , Jar.c , Jar.h, Milk.c , Milk.h
and the following makefile, named makePractice
, which is supposed to create two executables, Child
and CookieMonster
.
makefile:
CC = gcc # the compiler
CFLAGS = -Wall # the compiler flags
ChildObjects = Jar.o # object files for the Child executable
CookieMonsterObjects = Jar.o Milk.o #object files for the CookieMonster executable
all: Child CookieMonster # the first target. Both executables are created when
# 'make' is invoked with no target
# general rule for compiling a source and producing an object file
.c.o:
$(CC) $(CFLAGS) -c $<
# linking rule for the Child executable
Child: $(ChildObjects)
$(CC) $(CFLAGS) $(ChildObjects) -o Child
# linking rule for the CookieMonster executable
CookieMonster: $(CookieMonsterObjects)
$(CC) $(CFLAGS) $(CookieMonsterObjects) -o CookieMonster
# dependance rules for the .o files
Child.o: Child.c Cookie.h Jar.h
CookieMonster.o: CookieMonster.c Cookie.h Jar.h Milk.h
Jar.o: Jar.c Jar.h Cookie.h
Milk.o: Milk.c Milk.h
Cookie.o: Cookie.c Cookie.h
# gives the option to delete all the executable, .o and temporary files
clean:
rm -f *.o *~
When I try to use the makefile to create the executables, by running the following line in the shell
make -f makePractice
I get the following message:
make: Nothing to be done for `makefile'.
I don't understand what's wrong...
If you don't specify a target on the command-line, Make uses the first target defined in the makefile by default. In your case, that is makefile:
. But that doesn't do anything. So just remove makefile:
.
Your command line does not tell make
what you want to be made, so it defaults to trying to make the first explicitly named target in the makefile. That happens to be makefile
, at the very first line.
makefile:
Since there are no dependencies, there is no reason to do anything to remake that file. Therefore make
exits, happy at having obeyed your wish.
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