I am trying to compile this tool. Below is the beginning of its Makefile:
CC = gcc
CFLAGS = -Wall -O2 -D TRACES
DFLAGS = -g -Wall -o0
CPPFLAGS= $(INCLUDES:%=-I %)
LDFLAGS = $(LIBRARIES:%=-L %)
LDLIBS = $(USED_TOOLS:%=-l%)
MY_FILES =
INCLUDE_DIR = ~/include
TOOLBOX_INC = $(INCLUDE_DIR)/tools
TOOLBOX_LIB = $(TOOLBOX_INC)
USED_TOOLS = std_io stringutils
INCLUDES = $(TOOLBOX_INC)
LIBRARIES = $(TOOLBOX_LIB)
I also have ~/include/tools which after compiling includes std_io.o, libstd_io.a, stringutils.o and libstringutils.a
I am getting the following error:
gcc -L ~/include/tools rank.o counterexample.o -lstd_io -lstringutils -o rank
ld: library not found for -lstd_io
collect2: ld returned 1 exit status
make: *** [rank] Error 1
I am not sure if things are not included correctly, and why it is not finding the library files.
Edit: turns out I accidentally left a space between the -L and -I options. Also, the paths had to be expanded I guess. It's working now, thanks!
?= indicates to set the KDIR variable only if it's not set/doesn't have a value. For example: KDIR ?= "foo" KDIR ?= "bar" test: echo $(KDIR)
Since these files normally appear in the source directory, they should always appear in the source directory, not in the build directory. So Makefile rules to update them should put the updated files in the source directory.
some projects put their makefile in src/ subdirectory of the root directories of the projects, some projects put their makefiles in the root directory of the project.
All you need is a file called "makefile" or "Makefile". Comments Pound signs ("#") are comments to end of line. Variables CC = gcc. means that the variable CC contains "gcc". You access this variable by doing a $(CC) wherever you need it.
If you’re not finding a makefile even in the correct project directory, then run ./configure while you’re still inside of it followed by the make command.
It means that there isn’t a file called makefile or Makefile in your current working directory. Fortunately, that’s an easy error to fix. You may wish to try running the make command one more time in the current directory to see if the same error gets thrown at you.
Makefile not found. make: *** No rule to make target `Makefile'. Stop. 1. You don't have a Makefile in your project directory, in which case you can go to the project properties, change something (like a debugger, the press apply.
This 2 lines in Makefile get the full path and dir of the Makefile itself: mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST))) mkfile_dir := $(dir $(mkfile_path)) The piece of code gets you Makefile, finds its absolute path and the directory. It does not rely on your work directory at all.
The problem is the use of the tilde to mean "Home directory". A shell will do tilde expansion only if the tilde is the first nonquoted character in a word. Makefiles never do tilde expansion. Thus, in
gcc -L~/include ...
the shell does not perform tilde expansion and gcc will look for a directory named "~/include" in the current directory. But in
gcc -L ~/include ...
the shell does perform tilde expansion and gcc sees
gcc -L /usr/username/include ...
instead, which works as expected. The right thing to do is to never use tilde expansion for the home directory, but simply use $HOME appropriately in the Makefile, e.g.
INCLUDE_DIR = $$HOME/include
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