NMI and IRQ interruptions

Question

I am trying to find information about how the 6502 proccesor handles interruptions, but I am very confuse. I have seen some examples about it, but It is like a normal subrutine.

I have some experiences with the 8086 processor, and I remember that there are some codes to handle different interruptions.

Firstly, I will be very thankful if someone could explain me differences between NMI and IRQ with some code. And even more, If you get me more information about handling interruption for (for example) handling a keyboard interruption.

Answer 1

There are two separate interrupts: maskable and non-maskable. The 6502 will sample these one cycle before the end of each instruction.

If the NMI line has become active (it's edge triggered) then it will perform the NMI routine after this operation completes.

Otherwise, if the IRQ line is active (it's level triggered) and the interrupt disable flag isn't set then it will perform the IRQ routine after this operation completes.

In both cases it'll read the jump vector, push the current program counter and status register to the stack, set the interrupt disable bit and jump to wherever the vector indicated. From memory, that all takes seven cycles.

As well as pushing the status register there's a difference in who is considered responsible for incrementing the the program counter so you use RTI to return from an interrupt handler rather than RTS.

The NMI vector is read from FFFA/FFFBh, IRQ from FFFE/FFFFh. The reset vector is between and you could, at a distance, view reset as a kind of NMI that you can't return from.

BRK is supposed to sort of simulate an IRQ but doesn't do it very well.

So the intended arrangement is: NMIs for anything that should always be serviced now. IRQs for anything that's fine to wait a while. Quite a lot of micros don't wire up NMI at all because then you've always got to have a working handler, but that's far from universal.

Answer 2

The NMI (non-maskable interrupt) and IRQ (interrupt request) are separate physical pins on the CPU package.

When an interrupt is triggered, execution jumps to a memory location pointed to by 0xFFFE and 0xFFFF (for IRQ). For most processors, the registers should be pushed to the stack using:

PHA
PHX
PHY

SEI can be used to disable IRQs, but not NMIs. CLI will enable them again.

6502.org has a lot of tutorials.