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I want to include all .cpp and .cc files in the dependencies of a target using a wildcard.
Currently, I have to do the following:
all: main.cpp file1.cc file2.cc
g++ -O3 -o all main.cpp file1.cc file2.cc -I./include -L./lib
The following does not seem to be working:
all: %.cpp %.cc
g++ -O3 -o $@ $^ -I./include -L./lib
I get as error make: *** No rule to make target '%.cc', needed by 'all'. Stop.
726
If you want to do wildcard expansion in such places, you need to use the wildcard function, like this: $(wildcard pattern …) This string, used anywhere in a makefile, is replaced by a space-separated list of names of existing files that match one of the given file name patterns.
A dependency is a file that is used as input to create the target. A target often depends on several files. A command is an action that make carries out. A rule may have more than one command, each on its own line.
The file name of the target of the rule. If the target is an archive member, then ' $@ ' is the name of the archive file. In a pattern rule that has multiple targets (see Introduction to Pattern Rules), ' $@ ' is the name of whichever target caused the rule's recipe to be run.
Makefile for multiple targetsThis makefile is linked to the individual target makefiles. In other words when you run the multiple target makefile, it will then go and run all of the individual target makefiles.
targets := $(wildcard *.cpp) $(wildcard *.cc)
all: $(targets)
g++ $(targets)
this works for me
115
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