Loop through files in a Makefile

Question

So I have a C++ project with a directory full of test source files and I'm writing a makefile to make them all at once. Instead of compiling each file separately, is there a way I can cd into my test directory and loop through each file, compiling them one by one?

Thanks in advance for the help!

Answer 1

makefile implicit rule can be used to make all the files which is available in the folder. Also wildcard function can be used to get the .c or .cpp files which is available in particular folder.

%.o : %.cpp
    $(CC) -c $(CFLAGS) $(CPPFLAGS) $< -o $@

Example:

FILENAME:=  $(patsubst %.c,%.o,$(wildcard *.c))

all:$(FILENAME)
    @echo $(FILENAME)
##write exe generation script here

%.o : %.c
    gcc -c   $< -o $@